GadgetSeed  0.9.6
spi.c
[詳解]
1 /** @file
2  @brief STM32F4 SPIドライバ
3 
4  @date 2013.04.06
5  @author Takashi SHUDO
6 
7  @note
8 
9  SPI1
10  PA5 SPI1_SCK
11  PA6 SPI1_MISO
12  PA7 SPI1_MOSI
13  RX DMA2_Stream2
14  TX DMA2_Stream3
15 
16  SPI2
17  PB13 SPI2_SCK
18  PB14 SPI2_MISO
19  PB15 SPI2_MOSI
20  RX DMA1_Stream3
21  TX DMA1_Stream4
22 */
23 
24 #include "sysconfig.h"
25 #include "device.h"
26 #include "device/spi_ioctl.h"
27 #include "interrupt.h"
28 #include "tkprintf.h"
29 #include "task/event.h"
30 #include "task/mutex.h"
31 #include "task/syscall.h"
32 
33 //#define DEBUGKBITS 0x03
34 #include "dkprintf.h"
35 
36 
37 #define USE_MUTEX
38 #define USE_DMA
39 #define USE_DMA_INT
40 
41 #define VECTNUM_SPI1 51 // SPI1割り込み
42 #define VECTNUM_SPI2 52 // SPI2割り込み
43 #define VECTNUM_DMA2_RX 74 // DMA2_Stream2
44 #define VECTNUM_DMA2_TX 75 // DMA2_Stream3
45 #define VECTNUM_DMA1_RX 30 // DMA1_Stream3
46 #define VECTNUM_DMA1_TX 31 // DMA1_Stream4
47 
48 #define FCPU (GSC_CPU_CLOCK_HZ/2)
49 #define CLK_DEFAULT 400000UL // SCLKの周波数 400KHz
50 #define CLK_FP256 (FCPU/256) // SCLKの最小周波数
51 #define CLK_FP128 (FCPU/128)
52 #define CLK_FP64 (FCPU/64)
53 #define CLK_FP32 (FCPU/32)
54 #define CLK_FP16 (FCPU/16)
55 #define CLK_FP8 (FCPU/8)
56 #define CLK_FP4 (FCPU/4)
57 #define CLK_FP2 (FCPU/2) // SCLKの最大周波数
58 
59 /*
60  GPIOレジスタ
61 */
62 typedef struct st_reg_gpio {
63  unsigned int MODER;
64  unsigned int OTYPE;
65  unsigned int OSPEEDR;
66  unsigned int PUPDR;
67  unsigned int IDR;
68  unsigned int ODR;
69  unsigned int BSRR;
70  unsigned int LCKR;
71  unsigned int AFRL;
72  unsigned int AFRH;
73 } st_reg_gpio;
74 
75 #define GPIOA_BASE (0x40020000 + 0x000)
76 #define GPIOB_BASE (0x40020000 + 0x400)
77 #define GPIOC_BASE (0x40020000 + 0x800)
78 
79 #define GPIOA ((st_reg_gpio *)GPIOA_BASE)
80 #define GPIOB ((st_reg_gpio *)GPIOB_BASE)
81 #define GPIOC ((st_reg_gpio *)GPIOC_BASE)
82 
83 #define GPIO_MODE_BIT_IN 0x00UL // Input Mode
84 #define GPIO_MODE_BIT_OUT 0x01UL // Output Mode
85 #define GPIO_MODE_BIT_AF 0x02UL // Alternate functions Mode
86 #define GPIO_MODE_BIT_AN 0x03UL // Analog Mode
87 #define GPIO_MODE_BIT_ALL 0x03UL
88 
89 #define GPIO_OTYPE_BIT_PP 0x00UL // push-pull
90 #define GPIO_OTYPE_BIT_OD 0x01UL // open-drain
91 
92 #define GPIO_OSPEED_BIT_ALL 0x03UL
93 #define GPIO_OSPEED_BIT_100MHz 0x03UL
94 
95 #define GPIO_PUPDR_BIT_NOPULL 0x00UL // No pull-up, pull-down
96 #define GPIO_PUPDR_BIT_PUP 0x01UL // pull-up
97 #define GPIO_PUPDR_BIT_PDOWN 0x02UL // pull-down
98 #define GPIO_PUPDR_BIT_ALL 0x03UL
99 
100 #define GPIO_AFR_BIT_SPI12 0x05UL
101 #define GPIO_AFR_BIT_ALL 0x0FUL
102 
103 
104 /*
105  RCCレジスタ
106 */
107 #define RCC_AHB1ENR (*(volatile unsigned int *)0x40023830)
108 #define RCC_AHB1LPENR (*(volatile unsigned int *)0x40023850)
109 #define RCC_AHB1_BIT_GPIOA (1UL<<0)
110 #define RCC_AHB1_BIT_GPIOB (1UL<<1)
111 #define RCC_AHB1_BIT_GPIOC (1UL<<2)
112 #define RCC_AHB1_BIT_DMA1 (1UL<<21)
113 #define RCC_AHB1_BIT_DMA2 (1UL<<22)
114 
115 #define RCC_APB1ENR (*(volatile unsigned int *)0x40023840)
116 #define RCC_APB1_BIT_SPI2 (1UL<<14)
117 
118 #define RCC_APB2ENR (*(volatile unsigned int *)0x40023844)
119 #define RCC_APB2LPENR (*(volatile unsigned int *)0x40023864)
120 #define RCC_APB2_BIT_SPI1 (1UL<<12)
121 
122 /*
123  SPIレジスタ
124 */
125 typedef struct st_reg_spi {
126  unsigned int CR1; // + 0x00
127  unsigned int CR2; // + 0x04
128  unsigned int SR; // + 0x08
129  unsigned int DR; // + 0x0C
130  unsigned int CRCPR; // + 0x10
131  unsigned int RXCRCR; // + 0x14
132  unsigned int TXCRCR; // + 0x18
133  unsigned int I2SCFGR;// + 0x1C
134  unsigned int I2SPR; // + 0x20
135 } st_reg_spi;
136 
137 #define SPI1_BASE 0x40013000
138 #define SPI2_BASE 0x40003800
139 
140 #define SPI1 ((st_reg_spi *)SPI1_BASE)
141 #define SPI2 ((st_reg_spi *)SPI2_BASE)
142 
143 #define SPI_CR1_BIT_BIDIMODE (1UL<<15)
144 #define SPI_CR1_BIT_BIDIOE (1UL<<14)
145 #define SPI_CR1_BIT_CRCEN (1UL<<13)
146 #define SPI_CR1_BIT_CRCNEXT (1UL<<12)
147 #define SPI_CR1_BIT_DFF (1UL<<11)
148 #define SPI_CR1_BIT_RXONLY (1UL<<10)
149 #define SPI_CR1_BIT_SSM (1UL<<9)
150 #define SPI_CR1_BIT_SSI (1UL<<8)
151 #define SPI_CR1_BIT_LSBFIRST (1UL<<7)
152 #define SPI_CR1_BIT_SPE (1UL<<6)
153 #define SPI_CR1_BIT_BR_256 (7UL<<3)
154 #define SPI_CR1_BIT_MSTR (1UL<<2)
155 #define SPI_CR1_BIT_CPOL (1UL<<1)
156 #define SPI_CR1_BIT_CPHA (1UL<<0)
157 
158 #define SPI_CR2_BIT_TXEIE (1UL<<7)
159 #define SPI_CR2_BIT_RXNEIE (1UL<<6)
160 #define SPI_CR2_BIT_ERRIE (1UL<<5)
161 #define SPI_CR2_BIT_SSOE (1UL<<2)
162 #define SPI_CR2_BIT_TXDMAEN (1UL<<1)
163 #define SPI_CR2_BIT_RXDMAEN (1UL<<0)
164 
165 #define SPI_SR_BIT_BSY (1UL<<7)
166 #define SPI_SR_BIT_OVR (1UL<<6)
167 #define SPI_SR_BIT_MODF (1UL<<5)
168 #define SPI_SR_BIT_CRCERR (1UL<<4)
169 #define SPI_SR_BIT_UDR (1UL<<3)
170 #define SPI_SR_BIT_CHSIDE (1UL<<2)
171 #define SPI_SR_BIT_TXE (1UL<<1)
172 #define SPI_SR_BIT_RXNE (1UL<<0)
173 
174 #define SPI_I2SCFGR_BIT_I2SMOD (1UL<<11)
175 #define SPI_I2SCFGR_BIT_I2SE (1UL<<10)
176 #define SPI_I2SCFGR_BIT_I2SCFG (3UL<<8)
177 #define SPI_I2SCFGR_BIT_PCMSYNC (1UL<<7)
178 #define SPI_I2SCFGR_BIT_I2SSTD (3UL<<4)
179 #define SPI_I2SCFGR_BIT_CKPOLD (1UL<<3)
180 #define SPI_I2SCFGR_BIT_DATLEN (3UL<<1)
181 #define SPI_I2SCFGR_BIT_CHLEN (1UL<<0)
182 
183 /*
184  DMAレジスタ
185 */
186 typedef struct st_reg_dmacr {
187  unsigned int CR;
188  unsigned int NDTR;
189  unsigned int PAR;
190  unsigned int M0AR;
191  unsigned int M1AR;
192  unsigned int FCR;
193 } st_reg_dmacr;
194 
195 typedef struct st_reg_dma {
196  unsigned int LISR; // + 0x00
197  unsigned int HISR; // + 0x04
198  unsigned int LIFCR; // + 0x08
199  unsigned int HIFCR; // + 0x0C
200  st_reg_dmacr Sx[8];
201 } st_reg_dma;
202 
203 #define DMA1_BASE 0x40026000
204 #define DMA2_BASE 0x40026400
205 
206 #define DMA1 ((st_reg_dma *)DMA1_BASE)
207 #define DMA2 ((st_reg_dma *)DMA2_BASE)
208 
209 #define DMA_LISR_BIT_FEIF3 (1UL<<22)
210 #define DMA_LISR_BIT_TCIF3 (1UL<<27)
211 #define DMA_LISR_BIT_HTIF3 (1UL<<26)
212 #define DMA_LISR_BIT_TEIF3 (1UL<<25)
213 #define DMA_LISR_BIT_DMEIF3 (1UL<<24)
214 #define DMA_LISR_BIT_FEIF3 (1UL<<22)
215 
216 #define DMA_LISR_BIT_TCIF2 (1UL<<21)
217 #define DMA_LISR_BIT_HTIF2 (1UL<<20)
218 #define DMA_LISR_BIT_TEIF2 (1UL<<19)
219 #define DMA_LISR_BIT_DMEIF2 (1UL<<18)
220 #define DMA_LISR_BIT_FEIF2 (1UL<<16)
221 
222 #define DMA_HISR_BIT_TCIF4 (1UL<<5)
223 #define DMA_HISR_BIT_HTIF4 (1UL<<4)
224 #define DMA_HISR_BIT_TEIF4 (1UL<<3)
225 #define DMA_HISR_BIT_DMEIF4 (1UL<<2)
226 #define DMA_HISR_BIT_FEIF4 (1UL<<0)
227 
228 #define DMA_SxCR_BIT_EN (1UL<<0)
229 #define DMA_SxCR_BIT_DMEIE (1UL<<1)
230 #define DMA_SxCR_BIT_TEIE (1UL<<2)
231 #define DMA_SxCR_BIT_HTIE (1UL<<3)
232 #define DMA_SxCR_BIT_TCIE (1UL<<4)
233 #define DMA_SxCR_BIT_PFCTRL (1UL<<5)
234 #define DMA_SxCR_BIT_DIR_ALL (3UL<<6)
235 #define DMA_SxCR_BIT_DIR_P2M (0UL<<6)
236 #define DMA_SxCR_BIT_DIR_M2P (1UL<<6)
237 #define DMA_SxCR_BIT_DIR_M2M (2UL<<6)
238 #define DMA_SxCR_BIT_CIRC (1UL<<8)
239 #define DMA_SxCR_BIT_PINC (1UL<<9)
240 #define DMA_SxCR_BIT_MINC (1UL<<10)
241 #define DMA_SxCR_BIT_PSIZE_ALL (3UL<<11)
242 #define DMA_SxCR_BIT_PSIZE_BYTE (0UL<<11)
243 #define DMA_SxCR_BIT_PSIZE_HW (1UL<<11)
244 #define DMA_SxCR_BIT_PSIZE_WORD (2UL<<11)
245 #define DMA_SxCR_BIT_MSIZE_ALL (3UL<<13)
246 #define DMA_SxCR_BIT_MSIZE_BYTE (0UL<<13)
247 #define DMA_SxCR_BIT_MSIZE_HW (1UL<<13)
248 #define DMA_SxCR_BIT_MSIZE_WORD (2UL<<13)
249 #define DMA_SxCR_BIT_MSIZE_PINCOS (1UL<<15)
250 #define DMA_SxCR_BIT_PL_ALL (3UL<<16)
251 #define DMA_SxCR_BIT_PL_LOW (0UL<<16)
252 #define DMA_SxCR_BIT_PL_MEDIUM (1UL<<16)
253 #define DMA_SxCR_BIT_PL_HIGH (2UL<<16)
254 #define DMA_SxCR_BIT_PL_VHIGH (3UL<<16)
255 #define DMA_SxCR_BIT_DBM (1UL<<18)
256 #define DMA_SxCR_BIT_CT (1UL<<19)
257 #define DMA_SxCR_BIT_PBURST_ALL (3UL<<21)
258 #define DMA_SxCR_BIT_PBURST_SINGLE (0UL<<21)
259 #define DMA_SxCR_BIT_PBURST_INCR4 (1UL<<21)
260 #define DMA_SxCR_BIT_PBURST_INCR8 (2UL<<21)
261 #define DMA_SxCR_BIT_PBURST_INCR16 (3UL<<21)
262 #define DMA_SxCR_BIT_MBURST_ALL (3UL<<23)
263 #define DMA_SxCR_BIT_MBURST_SINGLE (0UL<<23)
264 #define DMA_SxCR_BIT_MBURST_INCR4 (1UL<<23)
265 #define DMA_SxCR_BIT_MBURST_INCR8 (2UL<<23)
266 #define DMA_SxCR_BIT_MBURST_INCR16 (3UL<<23)
267 #define DMA_SxCR_BIT_CHSEL_ALL (7UL<<25)
268 #define DMA_SxCR_BIT_CHSEL_CH0 (0UL<<25)
269 #define DMA_SxCR_BIT_CHSEL_CH1 (1UL<<25)
270 #define DMA_SxCR_BIT_CHSEL_CH2 (2UL<<25)
271 #define DMA_SxCR_BIT_CHSEL_CH3 (3UL<<25)
272 #define DMA_SxCR_BIT_CHSEL_CH4 (4UL<<25)
273 #define DMA_SxCR_BIT_CHSEL_CH5 (5UL<<25)
274 #define DMA_SxCR_BIT_CHSEL_CH6 (6UL<<25)
275 #define DMA_SxCR_BIT_CHSEL_CH7 (7UL<<25)
276 #define DMA_SxCR_BIT_CHSEL_SHIFT (25)
277 
278 #define DMA_SxFCR_BIT_FEIE (1UL<<7)
279 #define DMA_SxFCR_BIT_FS_ALL (7UL<<3)
280 #define DMA_SxFCR_BIT_DMDIS (1UL<<2)
281 #define DMA_SxFCR_BIT_FTH_ALL (3UL<<0)
282 #define DMA_SxFCR_BIT_FTH_1P4 (0UL<<0)
283 #define DMA_SxFCR_BIT_FTH_1P2 (1UL<<0)
284 #define DMA_SxFCR_BIT_FTH_3P4 (2UL<<0)
285 #define DMA_SxFCR_BIT_FTH_FULL (3UL<<0)
286 
287 #define NVIC_ISER0 (*(volatile unsigned int *)0xE000E100)
288 #define NVIC_ISER1 (*(volatile unsigned int *)0xE000E104)
289 
290 
291 struct st_spi_data {
292 #ifdef USE_MUTEX
293  struct st_mutex spimutex;
294 #endif
295 #ifdef USE_DMA_INT
296  struct st_event dma_evq;
297 #endif
298  st_reg_spi *spi;
299  st_reg_dma *dma;
300  unsigned char channel;
301  unsigned char rx_stream;
302  unsigned char tx_stream;
303 };
304 
305 static struct st_spi_data spi_data[2];
306 
307 const struct st_device spi1_device;
308 const struct st_device spi2_device;
309 
310 #ifdef USE_MUTEX
311 #define MUTEX_LOCK_TIMEOUT 1000
312 
313 void lock_spi(struct st_device *dev)
314 {
315  if(mutex_lock(&(((struct st_spi_data *)(dev->private_data))->spimutex),
316  MUTEX_LOCK_TIMEOUT) == 0) {
317  SYSERR_PRINT("%s lock timeout\n", dev->name);
318  }
319 }
320 
321 void unlock_spi(struct st_device *dev)
322 {
323  mutex_unlock(&(((struct st_spi_data *)(dev->private_data))->spimutex));
324 }
325 #else
326 #define lock_spi(x)
327 #define unlock_spi(x)
328 #endif
329 
330 
331 static void inthdr_spi1(unsigned int intnum, void *sp)
332 {
333 }
334 
335 static void inthdr_spi2(unsigned int intnum, void *sp)
336 {
337 }
338 
339 #ifdef USE_DMA_INT
340 static void inthdr_spi_dma2(unsigned int intnum, void *sp)
341 {
342  DMA2->LIFCR = DMA_LISR_BIT_TCIF2;
343 
344  if(intnum == VECTNUM_DMA2_RX) {
345  event_set_ISR(sp, &(((struct st_spi_data *)(spi1_device.private_data))->dma_evq));
346  } else {
347  SYSERR_PRINT("Invalid Interrupt(%d)\n", (int)intnum);
348  }
349 }
350 
351 static void inthdr_spi_dma1(unsigned int intnum, void *sp)
352 {
353  DMA1->LIFCR = DMA_LISR_BIT_TCIF3;
354 
355  if(intnum == VECTNUM_DMA1_RX) {
356  event_set_ISR(sp, &(((struct st_spi_data *)(spi2_device.private_data))->dma_evq));
357  } else {
358  SYSERR_PRINT("Invalid Interrupt(%d)\n", (int)intnum);
359  }
360 
361 }
362 #endif
363 
364 static void init_gpio(st_reg_gpio *gpio, int pin, int pup)
365 {
366  volatile st_reg_gpio *gpiox = gpio;
367 
368  if(pin < 8) {
369  gpiox->AFRL &= ~(GPIO_AFR_BIT_ALL << (4*pin));
370  gpiox->AFRL |= (GPIO_AFR_BIT_SPI12 << (4*pin));
371  } else {
372  gpiox->AFRH &= ~(GPIO_AFR_BIT_ALL << (4*(pin-8)));
373  gpiox->AFRH |= (GPIO_AFR_BIT_SPI12 << (4*(pin-8)));
374  }
375 
376  gpiox->MODER &= ~(GPIO_MODE_BIT_ALL << (2*pin));
377  gpiox->MODER |= (GPIO_MODE_BIT_AF << (2*pin));
378  gpiox->OSPEEDR &= ~(GPIO_OSPEED_BIT_ALL << (2*pin));
379  gpiox->OSPEEDR |= (GPIO_OSPEED_BIT_100MHz << (2*pin));
380  gpiox->OTYPE &= ~(1UL << pin);
381  gpiox->OTYPE |= (GPIO_OTYPE_BIT_PP << pin);
382  gpiox->PUPDR &= ~(GPIO_PUPDR_BIT_ALL << (2*pin));
383  if(pup != 0) {
384  gpiox->PUPDR |= (GPIO_PUPDR_BIT_PUP << (2*pin));
385  } else {
386  gpiox->PUPDR |= (GPIO_PUPDR_BIT_NOPULL << (2*pin));
387  }
388 }
389 
390 static void init_spi(struct st_device *dev)
391 {
392  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
393 #ifdef USE_DMA
394  volatile st_reg_dma *dmax = ((struct st_spi_data *)(dev->private_data))->dma;
395  int rx_stream = ((struct st_spi_data *)(dev->private_data))->rx_stream;
396  int tx_stream = ((struct st_spi_data *)(dev->private_data))->tx_stream;
397 #endif
398 
399  if(dev == &spi1_device) {
400  RCC_AHB1ENR |= RCC_AHB1_BIT_GPIOA; // GPIOA Clock enable
401 
402  // GPIOA PIN5,6,7 SPI Function
403  // MMCの場合は Pull UP
404  init_gpio(GPIOA, 5, 1);
405  init_gpio(GPIOA, 6, 1);
406  init_gpio(GPIOA, 7, 1);
407 
408  RCC_APB2ENR |= RCC_APB2_BIT_SPI1; // SPI1 Clock enable
409  } else if(dev == &spi2_device) {
410  RCC_AHB1ENR |= RCC_AHB1_BIT_GPIOB; // GPIOB Clock enable
411 #if 0
412  RCC_AHB1ENR |= RCC_AHB1_BIT_GPIOC; // GPIOC Clock enable
413 #endif
414 
415  // GPIOB PIN13,14,15 SPI Function
416 #ifdef SPI2SCK_PB10
417  init_gpio(GPIOB, 10, 0);
418 #else
419  init_gpio(GPIOB, 13, 0);
420 #endif
421 #if 0
422  init_gpio(GPIOC, 2, 0);
423  init_gpio(GPIOC, 3, 0);
424 #else
425  init_gpio(GPIOB, 14, 0);
426  init_gpio(GPIOB, 15, 0);
427 #endif
428 
429  RCC_APB1ENR |= RCC_APB1_BIT_SPI2; // SPI2 Clock enable
430  } else {
431  SYSERR_PRINT("Invalid device(%p)\n", dev);
432  }
433 
434 
435  spix->CR1 &= 0x3040;
436  spix->CR1 |= (SPI_CR1_BIT_MSTR | // Master Mode
437  SPI_CR1_BIT_SSM |
438  SPI_CR1_BIT_BR_256 |
439  SPI_CR1_BIT_SSI);
440 //#ifdef USE_ST7735R
441 #if 0
442  if(dev == &spi2_device) { // ST7735R用に暫定!!!
443  spix->CR1 |= (SPI_CR1_BIT_CPOL | SPI_CR1_BIT_CPHA);
444  }
445 #eles
446  if(dev == &spi2_device) { // ENC28J60用
447  spix->CR1 &= ~(SPI_CR1_BIT_CPOL | SPI_CR1_BIT_CPHA);
448 // spix->CR1 |= SPI_CR1_BIT_CPHA;
449  }
450 #endif
451  spix->I2SCFGR &= ~SPI_I2SCFGR_BIT_I2SMOD;
452  spix->CRCPR = 7;
453 
454  spix->CR1 |= SPI_CR1_BIT_SPE;
455 
456  while((spix->SR & SPI_SR_BIT_TXE) == 0) {
457  ;
458  }
459  spix->DR;
460 
461 #ifdef USE_DMA
462  if(dev == &spi1_device) {
463  RCC_AHB1ENR |= RCC_AHB1_BIT_DMA2; // DMA2 Clock enable
464 
465  dmax->Sx[rx_stream].CR &= ~DMA_SxCR_BIT_EN;
466  dmax->Sx[tx_stream].CR &= ~DMA_SxCR_BIT_EN;
467 
468  NVIC_ISER1 |= (1 << ((VECTNUM_DMA2_RX-16) % 32));
469  } else if(dev == &spi2_device) {
470  RCC_AHB1ENR |= RCC_AHB1_BIT_DMA1; // DMA1 Clock enable
471 
472  dmax->Sx[rx_stream].CR &= ~DMA_SxCR_BIT_EN;
473  dmax->Sx[tx_stream].CR &= ~DMA_SxCR_BIT_EN;
474 
475  NVIC_ISER0 |= (1 << ((VECTNUM_DMA1_RX-16) % 32));
476  } else {
477  SYSERR_PRINT("Invalid device(%p)\n", dev);
478  }
479 
480 #endif
481 }
482 
483 static int init_driver(struct st_device *dev)
484 {
485  void (* spi_ih)(unsigned int intnum, void *sp) = inthdr_spi1;
486  unsigned short spi_vn = VECTNUM_SPI1;
487 #ifdef USE_DMA_INT
488  void (* dma_ih)(unsigned int intnum, void *sp) = inthdr_spi_dma2;
489  unsigned short dma_vn = VECTNUM_DMA2_RX;
490 #endif
491 
492  if(dev == &spi1_device) {
493  spi_vn = VECTNUM_SPI1;
494  ((struct st_spi_data *)(dev->private_data))->spi = SPI1;
495  spi_ih = inthdr_spi1;
496 #ifdef USE_DMA_INT
497  ((struct st_spi_data *)(dev->private_data))->dma = DMA2;
498  ((struct st_spi_data *)(dev->private_data))->channel = 3;
499  ((struct st_spi_data *)(dev->private_data))->rx_stream = 2;
500  ((struct st_spi_data *)(dev->private_data))->tx_stream = 3;
501  dma_ih = inthdr_spi_dma2;
502  dma_vn = VECTNUM_DMA2_RX;
503 #endif
504 #ifdef USE_DMA_INT
505  register_interrupt(dma_vn, dma_ih);
506  eventqueue_register(&(((struct st_spi_data *)(dev->private_data))->dma_evq),
507  "spi1-dma", 0, 0, 0);
508 #endif
509 #ifdef USE_MUTEX
510  mutex_register(&(((struct st_spi_data *)(dev->private_data))->spimutex),
511  "spi1-mtx");
512 #endif
513  } else if(dev == &spi2_device) {
514  spi_vn = VECTNUM_SPI2;
515  ((struct st_spi_data *)(dev->private_data))->spi = SPI2;
516  spi_ih = inthdr_spi2;
517 #ifdef USE_DMA_INT
518  ((struct st_spi_data *)(dev->private_data))->dma = DMA1;
519  ((struct st_spi_data *)(dev->private_data))->channel = 0;
520  ((struct st_spi_data *)(dev->private_data))->rx_stream = 3;
521  ((struct st_spi_data *)(dev->private_data))->tx_stream = 4;
522  dma_ih = inthdr_spi_dma1;
523  dma_vn = VECTNUM_DMA1_RX;
524 #endif
525 #ifdef USE_DMA_INT
526  register_interrupt(dma_vn, dma_ih);
527  eventqueue_register(&(((struct st_spi_data *)(dev->private_data))->dma_evq),
528  "spi2-dma", 0, 0, 0);
529 #endif
530 #ifdef USE_MUTEX
531  mutex_register(&(((struct st_spi_data *)(dev->private_data))->spimutex),
532  "spi2-mtx");
533 #endif
534  } else {
535  SYSERR_PRINT("Unknown SPI device(%p)\n", dev);
536  return -1;
537  }
538 
539  register_interrupt(spi_vn, spi_ih);
540 
541  init_spi(dev);
542 
543  return 0;
544 }
545 
546 #define SPI_RETRY_TIME 1000000
547 
548 static int spi_readbyte(struct st_device *dev, unsigned char *rd)
549 {
550  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
551  int i = SPI_RETRY_TIME;
552 
553  spix->DR = 0xFF;
554 
555  while((spix->SR & SPI_SR_BIT_TXE) == 0) {
556  i --;
557  if(i == 0) {
558  SYSERR_PRINT("TXE timeout\n");
559  break;
560  }
561  }
562 
563  while((spix->SR & SPI_SR_BIT_RXNE) == 0) {
564  i --;
565  if(i == 0) {
566  SYSERR_PRINT("RXNE timeout\n");
567  break;
568  }
569  }
570 
571  while(spix->SR & SPI_SR_BIT_BSY) {
572  i --;
573  if(i == 0) {
574  SYSERR_PRINT("BSY timeout\n");
575  break;
576  }
577  }
578 
579  *rd = spix->DR;
580 
581  DKPRINTF(0x02, "SPI1 RD = %02X\n", *rd);
582 
583  return 1;
584 }
585 
586 #define SPI_WAIT_TIME 500
587 #ifdef USE_DMA
588 
589 static int spi_transblock(struct st_device *dev, unsigned char *rd, long size,
590  int dir_read)
591 {
592  static const unsigned char dummy_data = 0xFF;
593 
594  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
595  volatile st_reg_dma *dmax = ((struct st_spi_data *)(dev->private_data))->dma;
596  unsigned int channel = ((struct st_spi_data *)(dev->private_data))->channel;
597  int rx_stream = ((struct st_spi_data *)(dev->private_data))->rx_stream;
598  int tx_stream = ((struct st_spi_data *)(dev->private_data))->tx_stream;
599  unsigned int tmp;
600  int rt = 0;
601  int err = 0;
602 
603  DKPRINTF(0x01, "SPI DMA *data=%p, size=%ld, W(0)/R(1)=%d\n", rd, size, dir_read);
604 
605  while(dmax->Sx[tx_stream].CR & DMA_SxCR_BIT_EN) {
606  ;
607  }
608 
609  spix->CR1 &= ~SPI_CR1_BIT_DFF; // 8 bit data frame
610 
611  tmp = dmax->Sx[rx_stream].CR;
612  tmp &= ~(DMA_SxCR_BIT_CHSEL_ALL | DMA_SxCR_BIT_MBURST_ALL |
613  DMA_SxCR_BIT_PBURST_ALL | DMA_SxCR_BIT_PL_ALL |
614  DMA_SxCR_BIT_MSIZE_ALL | DMA_SxCR_BIT_PSIZE_ALL |
615  DMA_SxCR_BIT_MINC | DMA_SxCR_BIT_PINC |
616  DMA_SxCR_BIT_CIRC | DMA_SxCR_BIT_DIR_ALL);
617  tmp |= ((channel << DMA_SxCR_BIT_CHSEL_SHIFT) |
618  DMA_SxCR_BIT_DIR_P2M |
619  DMA_SxCR_BIT_PSIZE_BYTE |
620  DMA_SxCR_BIT_MSIZE_BYTE |
621  DMA_SxCR_BIT_PL_HIGH |
622  DMA_SxCR_BIT_PBURST_SINGLE |
623  DMA_SxCR_BIT_MBURST_SINGLE);
624  if(dir_read) {
625  tmp |= DMA_SxCR_BIT_MINC;
626  }
627  dmax->Sx[rx_stream].CR = tmp;
628 
629  tmp = dmax->Sx[rx_stream].FCR;
630  tmp &= ~(DMA_SxFCR_BIT_DMDIS | DMA_SxFCR_BIT_FTH_ALL);
631  tmp |= DMA_SxFCR_BIT_FTH_FULL;
632  tmp = dmax->Sx[rx_stream].FCR = tmp;
633 
634  dmax->Sx[rx_stream].NDTR = size;
635  dmax->Sx[rx_stream].PAR = (unsigned int)&(spix->DR);
636  if(dir_read) {
637  dmax->Sx[rx_stream].M0AR = (unsigned int)rd;
638  } else {
639  dmax->Sx[rx_stream].M0AR = (unsigned int)(&dummy_data);
640  }
641 
642  tmp = dmax->Sx[tx_stream].CR;
643  tmp &= ~(DMA_SxCR_BIT_CHSEL_ALL | DMA_SxCR_BIT_MBURST_ALL |
644  DMA_SxCR_BIT_PBURST_ALL | DMA_SxCR_BIT_PL_ALL |
645  DMA_SxCR_BIT_MSIZE_ALL | DMA_SxCR_BIT_PSIZE_ALL |
646  DMA_SxCR_BIT_MINC | DMA_SxCR_BIT_PINC |
647  DMA_SxCR_BIT_CIRC | DMA_SxCR_BIT_DIR_ALL);
648  tmp |= ((channel << DMA_SxCR_BIT_CHSEL_SHIFT) |
649  DMA_SxCR_BIT_DIR_M2P |
650  DMA_SxCR_BIT_PSIZE_BYTE |
651  DMA_SxCR_BIT_MSIZE_BYTE |
652  DMA_SxCR_BIT_PL_HIGH |
653  DMA_SxCR_BIT_PBURST_SINGLE |
654  DMA_SxCR_BIT_MBURST_SINGLE);
655  if(dir_read == 0) {
656  tmp |= DMA_SxCR_BIT_MINC;
657  }
658  dmax->Sx[tx_stream].CR = tmp;
659 
660  tmp = dmax->Sx[tx_stream].FCR;
661  tmp &= ~(DMA_SxFCR_BIT_DMDIS | DMA_SxFCR_BIT_FTH_ALL);
662  tmp |= DMA_SxFCR_BIT_FTH_FULL;
663  dmax->Sx[tx_stream].FCR = tmp;
664 
665  dmax->Sx[tx_stream].NDTR = size;
666  dmax->Sx[tx_stream].PAR = (unsigned int)&(spix->DR);
667  if(dir_read) {
668  dmax->Sx[tx_stream].M0AR = (unsigned int)(&dummy_data);
669  } else {
670  dmax->Sx[tx_stream].M0AR = (unsigned int)rd;
671  }
672 
673  spix->CR2 |= (SPI_CR2_BIT_RXDMAEN | SPI_CR2_BIT_TXDMAEN);
674 
675 #ifdef USE_DMA_INT
676  event_clear(&(((struct st_spi_data *)(dev->private_data))->dma_evq));
677 #endif
678  dmax->Sx[rx_stream].CR |= (DMA_SxCR_BIT_TCIE | DMA_SxCR_BIT_TEIE);
679  dmax->Sx[rx_stream].CR |= DMA_SxCR_BIT_EN;
680  dmax->Sx[tx_stream].CR |= DMA_SxCR_BIT_EN;
681 
682 #ifdef USE_DMA_INT
683  rt = event_wait(&(((struct st_spi_data *)(dev->private_data))->dma_evq),
684  0, SPI_WAIT_TIME);
685  if(rt == 0) {
686  err = 1;
687  SYSERR_PRINT("SPI DMA timeout(%ld)\n", rt);
688  }
689 #else
690  if(dev == &spi1_device) {
691  while((dmax->LISR & DMA_LISR_BIT_TCIF3) == 0) {
692  ;
693  }
694  } else if(dev == &spi2_device) {
695  while((dmax->HISR & DMA_HISR_BIT_TCIF4) == 0) {
696  ;
697  }
698  } else {
699  SYSERR_PRINT("Invalid device(%p)\n", dev);
700  }
701 
702 #endif
703 
704  dmax->Sx[rx_stream].CR &= ~DMA_SxCR_BIT_EN;
705  dmax->Sx[tx_stream].CR &= ~DMA_SxCR_BIT_EN;
706  spix->CR2 &= ~(SPI_CR2_BIT_RXDMAEN | SPI_CR2_BIT_TXDMAEN);
707 
708 #ifndef USE_DMA_INT
709  if(dev == &spi1_device) {
710  dmax->LIFCR = DMA_LISR_BIT_TCIF2;
711  } else if(dev == &spi2_device) {
712  dmax->LIFCR = DMA_LISR_BIT_TCIF3;
713  } else {
714  SYSERR_PRINT("Invalid device(%p)\n", dev);
715  }
716 
717 #endif
718  if(dev == &spi1_device) {
719  dmax->LIFCR = DMA_LISR_BIT_TCIF3;
720  } else if(dev == &spi2_device) {
721  dmax->HIFCR = DMA_HISR_BIT_TCIF4;
722  } else {
723  SYSERR_PRINT("Invalid device(%p)\n", dev);
724  }
725 
726 
727 #ifdef DEBUGKBITS
728  {
729  int i;
730  for(i=0; i<size; i++) {
731  DKPRINTF(0x02, "%02X ", rd[i]);
732  }
733  }
734 #endif
735 
736  if(err != 0) {
737  size = -1;
738  }
739 
740  return size;
741 }
742 
743 static int spi_write_cont_word(struct st_device *dev, unsigned short data,
744  long size)
745 {
746  static const unsigned char dummy_data = 0xFF;
747  volatile unsigned int wdata = data;
748 
749  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
750  volatile st_reg_dma *dmax = ((struct st_spi_data *)(dev->private_data))->dma;
751  unsigned int channel = ((struct st_spi_data *)(dev->private_data))->channel;
752  int rx_stream = ((struct st_spi_data *)(dev->private_data))->rx_stream;
753  int tx_stream = ((struct st_spi_data *)(dev->private_data))->tx_stream;
754  unsigned int tmp;
755  int rt = 0;
756 
757  while(dmax->Sx[tx_stream].CR & DMA_SxCR_BIT_EN) {
758  ;
759  }
760 
761  spix->CR1 |= SPI_CR1_BIT_DFF; // 16 bit data frame
762 
763  tmp = dmax->Sx[rx_stream].CR;
764  tmp &= ~(DMA_SxCR_BIT_CHSEL_ALL | DMA_SxCR_BIT_MBURST_ALL |
765  DMA_SxCR_BIT_PBURST_ALL | DMA_SxCR_BIT_PL_ALL |
766  DMA_SxCR_BIT_MSIZE_ALL | DMA_SxCR_BIT_PSIZE_ALL |
767  DMA_SxCR_BIT_MINC | DMA_SxCR_BIT_PINC |
768  DMA_SxCR_BIT_CIRC | DMA_SxCR_BIT_DIR_ALL);
769  tmp |= ((channel << DMA_SxCR_BIT_CHSEL_SHIFT) |
770  DMA_SxCR_BIT_DIR_P2M |
771  DMA_SxCR_BIT_PSIZE_WORD |
772  DMA_SxCR_BIT_MSIZE_WORD |
773  DMA_SxCR_BIT_PL_HIGH |
774  DMA_SxCR_BIT_PBURST_SINGLE |
775  DMA_SxCR_BIT_MBURST_SINGLE);
776  dmax->Sx[rx_stream].CR = tmp;
777 
778  tmp = dmax->Sx[rx_stream].FCR;
779  tmp &= ~(DMA_SxFCR_BIT_DMDIS | DMA_SxFCR_BIT_FTH_ALL);
780  tmp |= DMA_SxFCR_BIT_FTH_FULL;
781  tmp = dmax->Sx[rx_stream].FCR = tmp;
782 
783  dmax->Sx[rx_stream].NDTR = size * 2; // WORD = 2 bytes
784  dmax->Sx[rx_stream].PAR = (unsigned int)&(spix->DR);
785  dmax->Sx[rx_stream].M0AR = (unsigned int)(&dummy_data);
786 
787  tmp = dmax->Sx[tx_stream].CR;
788  tmp &= ~(DMA_SxCR_BIT_CHSEL_ALL | DMA_SxCR_BIT_MBURST_ALL |
789  DMA_SxCR_BIT_PBURST_ALL | DMA_SxCR_BIT_PL_ALL |
790  DMA_SxCR_BIT_MSIZE_ALL | DMA_SxCR_BIT_PSIZE_ALL |
791  DMA_SxCR_BIT_MINC | DMA_SxCR_BIT_PINC |
792  DMA_SxCR_BIT_CIRC | DMA_SxCR_BIT_DIR_ALL);
793  tmp |= ((channel << DMA_SxCR_BIT_CHSEL_SHIFT) |
794  DMA_SxCR_BIT_DIR_M2P |
795  DMA_SxCR_BIT_PSIZE_WORD |
796  DMA_SxCR_BIT_MSIZE_WORD |
797  DMA_SxCR_BIT_PL_HIGH |
798  DMA_SxCR_BIT_PBURST_SINGLE |
799  DMA_SxCR_BIT_MBURST_SINGLE);
800  dmax->Sx[tx_stream].CR = tmp;
801 
802  tmp = dmax->Sx[tx_stream].FCR;
803  tmp &= ~(DMA_SxFCR_BIT_DMDIS | DMA_SxFCR_BIT_FTH_ALL);
804  tmp |= DMA_SxFCR_BIT_FTH_FULL;
805  dmax->Sx[tx_stream].FCR = tmp;
806 
807  dmax->Sx[tx_stream].NDTR = size * 2; // WORD = 2 bytes
808  dmax->Sx[tx_stream].PAR = (unsigned int)&(spix->DR);
809  dmax->Sx[tx_stream].M0AR = (unsigned int)&wdata;
810 
811  spix->CR2 |= (SPI_CR2_BIT_RXDMAEN | SPI_CR2_BIT_TXDMAEN);
812 
813 #ifdef USE_DMA_INT
814  event_clear(&(((struct st_spi_data *)(dev->private_data))->dma_evq));
815 #endif
816  dmax->Sx[rx_stream].CR |= (DMA_SxCR_BIT_TCIE | DMA_SxCR_BIT_TEIE);
817  dmax->Sx[rx_stream].CR |= DMA_SxCR_BIT_EN;
818  dmax->Sx[tx_stream].CR |= DMA_SxCR_BIT_EN;
819 
820 #ifdef USE_DMA_INT
821  rt = event_wait(&(((struct st_spi_data *)(dev->private_data))->dma_evq),
822  0, SPI_WAIT_TIME);
823  if(rt == 0) {
824  SYSERR_PRINT("SPI DMA timeout(%d)\n", rt);
825  }
826 #else
827  if(dev == &spi1_device) {
828  while((dmax->LISR & DMA_LISR_BIT_TCIF3) == 0) {
829  ;
830  }
831  } else if(dev == &spi2_device) {
832  while((dmax->HISR & DMA_HISR_BIT_TCIF4) == 0) {
833  ;
834  }
835  } else {
836  SYSERR_PRINT("Invalid device(%p)\n", dev);
837  }
838 
839 #endif
840 
841  dmax->Sx[rx_stream].CR &= ~DMA_SxCR_BIT_EN;
842  dmax->Sx[tx_stream].CR &= ~DMA_SxCR_BIT_EN;
843  spix->CR2 &= ~(SPI_CR2_BIT_RXDMAEN | SPI_CR2_BIT_TXDMAEN);
844 
845 #ifndef USE_DMA_INT
846  if(dev == &spi1_device) {
847  dmax->LIFCR = DMA_LISR_BIT_TCIF2;
848  } else if(dev == &spi2_device) {
849  dmax->LIFCR = DMA_LISR_BIT_TCIF3;
850  }
851 #endif
852  if(dev == &spi1_device) {
853  dmax->LIFCR = DMA_LISR_BIT_TCIF3;
854  } else if(dev == &spi2_device) {
855  dmax->HIFCR = DMA_HISR_BIT_TCIF4;
856  } else {
857  SYSERR_PRINT("Invalid device(%p)\n", dev);
858  }
859 
860  return size;
861 }
862 #endif
863 
864 static int spi_writebyte(struct st_device *dev, unsigned char data)
865 {
866  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
867  int i = SPI_WAIT_TIME;
868  volatile unsigned short tmp;
869 
870  spix->CR1 &= ~SPI_CR1_BIT_DFF; // 8 bit data frame
871 
872  spix->DR = data;
873 
874  while((spix->SR & SPI_SR_BIT_TXE) == 0) {
875  i --;
876  if(i == 0) {
877  SYSERR_PRINT("TXE timeout\n");
878  break;
879  }
880  }
881 
882  while((spix->SR & SPI_SR_BIT_RXNE) == 0) {
883  i --;
884  if(i == 0) {
885  SYSERR_PRINT("RXNE timeout\n");
886  break;
887  }
888  }
889 
890  while(spix->SR & SPI_SR_BIT_BSY) {
891  i --;
892  if(i == 0) {
893  SYSERR_PRINT("BSY timeout\n");
894  break;
895  }
896  }
897 
898  tmp = spix->DR;
899  (void)tmp;
900 
901  return 1;
902 }
903 
904 static int spi_writeword(struct st_device *dev, unsigned short data)
905 {
906  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
907  int i = SPI_WAIT_TIME;
908  volatile unsigned short tmp;
909 
910  spix->CR1 |= SPI_CR1_BIT_DFF; // 16 bit data frame
911 
912  spix->DR = data;
913 
914  while((spix->SR & SPI_SR_BIT_TXE) == 0) {
915  i --;
916  if(i == 0) {
917  SYSERR_PRINT("TXE timeout\n");
918  break;
919  }
920  }
921 
922  while((spix->SR & SPI_SR_BIT_RXNE) == 0) {
923  i --;
924  if(i == 0) {
925  SYSERR_PRINT("RXNE timeout\n");
926  break;
927  }
928  }
929 
930  while(spix->SR & SPI_SR_BIT_BSY) {
931  i --;
932  if(i == 0) {
933  SYSERR_PRINT("BSY timeout\n");
934  break;
935  }
936  }
937 
938  tmp = spix->DR;
939  (void)tmp;
940 
941  return 1;
942 }
943 
944 /*
945  *
946  */
947 
948 static int spi_register(struct st_device *dev, char *param)
949 {
950  if(init_driver(dev)) {
951  return -1;
952  }
953 
954  return 0;
955 }
956 
957 static int spi_getc(struct st_device *dev, unsigned char *rd)
958 {
959  int rtn;
960 
961  lock_spi(dev);
962 
963  rtn = spi_readbyte(dev, rd);
964 
965  unlock_spi(dev);
966 
967  return rtn;
968 }
969 
970 static int spi_read(struct st_device *dev, void *data, unsigned int size)
971 {
972  int len = 0;
973  int rtn = 0;
974 
975  lock_spi(dev);
976 
977 #ifdef USE_DMA
978  rtn = spi_transblock(dev, data, size, 1);
979  len = size;
980 #else
981  while(size) {
982  long rtn = spi_readbyte(dev, data);
983  if(rtn == 0) {
984  break;
985  }
986  DKPRINTF(0x02, "%02X ", *data);
987  data ++;
988  size --;
989  len ++;
990  }
991 #endif
992 
993  unlock_spi(dev);
994 
995  if(rtn < 0) {
996  len = -1;
997  }
998 
999  return len;
1000 }
1001 
1002 static int spi_putc(struct st_device *dev, unsigned char ch)
1003 {
1004  int rtn;
1005 
1006  lock_spi(dev);
1007 
1008  rtn = spi_writebyte(dev, ch);
1009 
1010  unlock_spi(dev);
1011 
1012  return rtn;
1013 }
1014 
1015 static int spi_write(struct st_device *dev, const void *data, unsigned int size)
1016 {
1017  int len = 0;
1018  int rtn = 0;
1019 
1020  lock_spi(dev);
1021 
1022 #ifdef USE_DMA
1023  rtn = spi_transblock(dev, (unsigned char *)data, size, 0);
1024  len = size;
1025 #else
1026  while(size) {
1027  long rtn = spi_writebyte(dev, *data);
1028  if(rtn == 0) {
1029  break;
1030  }
1031  data ++;
1032  size --;
1033  len ++;
1034  }
1035 #endif
1036 
1037  unlock_spi(dev);
1038 
1039  if(rtn < 0) {
1040  len = -1;
1041  }
1042 
1043  return len;
1044 }
1045 
1046 static int spi_ioctl(struct st_device *dev, unsigned int com, unsigned int arg, void *param)
1047 {
1048  volatile st_reg_spi *spix = ((struct st_spi_data *)(dev->private_data))->spi;
1049  int rtn = 0;
1050  int br = 7;
1051 
1052  lock_spi(dev);
1053 
1054  switch(com) {
1055  case IOCMD_SPI_SPEED: // 転送速度を設定する
1056  DKFPRINTF(0x01, "arg = %ld\n", arg);
1057  if(CLK_FP2 <= arg) {
1058  br = 0;
1059  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP2);
1060  } else
1061  if((CLK_FP4 <= arg) && (arg < CLK_FP2)) {
1062  br = 1;
1063  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP4);
1064  } else
1065  if((CLK_FP8 <= arg) && (arg < CLK_FP4)) {
1066  br = 2;
1067  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP8);
1068  } else
1069  if((CLK_FP16 <= arg) && (arg < CLK_FP8)) {
1070  br = 3;
1071  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP16);
1072  } else
1073  if((CLK_FP32 <= arg) && (arg < CLK_FP16)) {
1074  br = 4;
1075  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP32);
1076  } else
1077  if((CLK_FP64 <= arg) && (arg < CLK_FP32)) {
1078  br = 5;
1079  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP64);
1080  } else
1081  if((CLK_FP128 <= arg) && (arg < CLK_FP64)) {
1082  br = 6;
1083  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP128);
1084  } else
1085  if(arg < CLK_FP128) {
1086  br = 7;
1087  DKPRINTF(0x01, "BR = %d(SPEED = %d bps)\n", br, (int)CLK_FP256);
1088  }
1089 
1090  spix->CR1 &= ~SPI_CR1_BIT_SPE;
1091  spix->CR1 = ((spix->CR1 & ~SPI_CR1_BIT_BR_256) |
1092  (br<<3)); // fcpu/br
1093  spix->CR1 |= SPI_CR1_BIT_SPE;
1094  DKPRINTF(0x01, "SPIx_CR1 = %08X\n", (int)spix->CR1);
1095  break;
1096 
1097  case IOCMD_SPI_FORCE_UNLOCK: // 強制的にアンロック
1098  unlock_spi(dev);
1099  break;
1100 
1101  case IOCMD_SPI_WRITE_WORD:
1102  rtn = spi_writeword(dev, arg & 0xffff);
1103  break;
1104 
1105  case IOCMD_SPI_WRITE_CONT_WORD:
1106  rtn = spi_write_cont_word(dev, arg & 0xffff,
1107  (arg >> 16) & 0xffff);
1108  break;
1109 
1110  default:
1111  SYSERR_PRINT("Unknown ioctl(%08lX)\n", com);
1112  break;
1113  }
1114 
1115  unlock_spi(dev);
1116 
1117  return rtn;
1118 }
1119 
1120 static int spi_suspend(struct st_device *dev)
1121 {
1122  return 0;
1123 }
1124 
1125 static int spi_resume(struct st_device *dev)
1126 {
1127  init_spi(dev);
1128 
1129  return 0;
1130 }
1131 
1132 const struct st_device spi1_device = {
1133  .name = DEF_DEV_NAME_SPI,
1134  .explan = "STM32F4 SPI1",
1135  .private_data = (void *)&spi_data[0],
1136  .register_dev = spi_register,
1137  .read = spi_read,
1138  .getc = spi_getc,
1139  .write = spi_write,
1140  .putc = spi_putc,
1141  .ioctl = spi_ioctl,
1142  .suspend = spi_suspend,
1143  .resume = spi_resume,
1144 };
1145 
1146 const struct st_device spi2_device = {
1147  .name = DEF_DEV_NAME_SPI "1",
1148  .explan = "STM32F4 SPI2",
1149  .private_data = (void *)&spi_data[1],
1150  .register_dev = spi_register,
1151  .read = spi_read,
1152  .getc = spi_getc,
1153  .write = spi_write,
1154  .putc = spi_putc,
1155  .ioctl = spi_ioctl,
1156  .suspend = spi_suspend,
1157  .resume = spi_resume,
1158 };
IOCMD_SPI_WRITE_CONT_WORD
#define IOCMD_SPI_WRITE_CONT_WORD
2バイトデータを読み出す
Definition: spi_ioctl.h:40
mutex_register
void mutex_register(struct st_mutex *mutex, const char *name)
MUTEXを登録する
Definition: syscall_api.c:497
eventqueue_register
void eventqueue_register(struct st_event *evtque, const char *name, void *args, unsigned int size, int count)
イベントキューを登録する
Definition: syscall_api.c:339
st_device::private_data
void * private_data
ドライバ固有データポインタ
Definition: device.h:29
spi_ioctl.h
SPIドライバ ioctl 用マクロ定義
CR
#define CR
lineedit.stat
Definition: lineedit.c:37
IOCMD_SPI_SPEED
#define IOCMD_SPI_SPEED
com : 転送速度を設定する, arg : 転送速度(bps)
Definition: spi_ioctl.h:18
mutex_lock
int mutex_lock(struct st_mutex *mutex, unsigned int timeout)
MUTEXをロックする
Definition: syscall_api.c:517
suspend
int suspend(void)
全デバイスを休止状態にする
Definition: device.c:634
mutex_unlock
int mutex_unlock(struct st_mutex *mutex)
MUTEXをアンロックする
Definition: syscall_api.c:543
tkprintf.h
カーネル用機能限定printf
IOCMD_SPI_WRITE_WORD
#define IOCMD_SPI_WRITE_WORD
2バイトデータを書き込む
Definition: spi_ioctl.h:36
DEF_DEV_NAME_SPI
#define DEF_DEV_NAME_SPI
標準SPIマスターコントローラデバイス名
Definition: spi_ioctl.h:15
st_mutex
MUTEX
Definition: mutex.h:13
st_event
イベント
Definition: event.h:15
syscall.h
システムコール
interrupt.h
割り込みハンドラ
mutex.h
MUTEX制御
event_clear
void event_clear(struct st_event *evtque)
イベントキューに登録されているイベントを削除する
Definition: syscall_api.c:430
event.h
イベント待ちタスクキューの操作
resume
int resume(void)
全デバイスを活性化する
Definition: device.c:655
event_set_ISR
void event_set_ISR(void *sp, struct st_event *evtque)
イベント待ちタスクを起動する
Definition: task.c:879
device.h
デバイスドライバAPI
st_device
デバイスドライバ構造体
Definition: device.h:25
dkprintf.h
カーネル、ドライバ(非タスク)デバッグ用マクロ
IOCMD_SPI_FORCE_UNLOCK
#define IOCMD_SPI_FORCE_UNLOCK
強制的にアンロック
Definition: spi_ioctl.h:33
st_device::name
char name[MAX_DEVNAMELRN]
デバイス名文字列
Definition: device.h:26
event_wait
int event_wait(struct st_event *evtque, void *argp, unsigned int timeout)
タスクをイベント待ち状態にする
Definition: syscall_api.c:364