|
#define | USE_MUTEX |
|
#define | USE_DMA |
|
#define | USE_DMA_INT |
|
#define | VECTNUM_SPI1 51 |
|
#define | VECTNUM_SPI2 52 |
|
#define | VECTNUM_DMA2_RX 74 |
|
#define | VECTNUM_DMA2_TX 75 |
|
#define | VECTNUM_DMA1_RX 30 |
|
#define | VECTNUM_DMA1_TX 31 |
|
#define | FCPU (GSC_CPU_CLOCK_HZ/2) |
|
#define | CLK_DEFAULT 400000UL |
|
#define | CLK_FP256 (FCPU/256) |
|
#define | CLK_FP128 (FCPU/128) |
|
#define | CLK_FP64 (FCPU/64) |
|
#define | CLK_FP32 (FCPU/32) |
|
#define | CLK_FP16 (FCPU/16) |
|
#define | CLK_FP8 (FCPU/8) |
|
#define | CLK_FP4 (FCPU/4) |
|
#define | CLK_FP2 (FCPU/2) |
|
#define | GPIOA_BASE (0x40020000 + 0x000) |
|
#define | GPIOB_BASE (0x40020000 + 0x400) |
|
#define | GPIOC_BASE (0x40020000 + 0x800) |
|
#define | GPIOA ((st_reg_gpio *)GPIOA_BASE) |
|
#define | GPIOB ((st_reg_gpio *)GPIOB_BASE) |
|
#define | GPIOC ((st_reg_gpio *)GPIOC_BASE) |
|
#define | GPIO_MODE_BIT_IN 0x00UL |
|
#define | GPIO_MODE_BIT_OUT 0x01UL |
|
#define | GPIO_MODE_BIT_AF 0x02UL |
|
#define | GPIO_MODE_BIT_AN 0x03UL |
|
#define | GPIO_MODE_BIT_ALL 0x03UL |
|
#define | GPIO_OTYPE_BIT_PP 0x00UL |
|
#define | GPIO_OTYPE_BIT_OD 0x01UL |
|
#define | GPIO_OSPEED_BIT_ALL 0x03UL |
|
#define | GPIO_OSPEED_BIT_100MHz 0x03UL |
|
#define | GPIO_PUPDR_BIT_NOPULL 0x00UL |
|
#define | GPIO_PUPDR_BIT_PUP 0x01UL |
|
#define | GPIO_PUPDR_BIT_PDOWN 0x02UL |
|
#define | GPIO_PUPDR_BIT_ALL 0x03UL |
|
#define | GPIO_AFR_BIT_SPI12 0x05UL |
|
#define | GPIO_AFR_BIT_ALL 0x0FUL |
|
#define | RCC_AHB1ENR (*(volatile unsigned int *)0x40023830) |
|
#define | RCC_AHB1LPENR (*(volatile unsigned int *)0x40023850) |
|
#define | RCC_AHB1_BIT_GPIOA (1UL<<0) |
|
#define | RCC_AHB1_BIT_GPIOB (1UL<<1) |
|
#define | RCC_AHB1_BIT_GPIOC (1UL<<2) |
|
#define | RCC_AHB1_BIT_DMA1 (1UL<<21) |
|
#define | RCC_AHB1_BIT_DMA2 (1UL<<22) |
|
#define | RCC_APB1ENR (*(volatile unsigned int *)0x40023840) |
|
#define | RCC_APB1_BIT_SPI2 (1UL<<14) |
|
#define | RCC_APB2ENR (*(volatile unsigned int *)0x40023844) |
|
#define | RCC_APB2LPENR (*(volatile unsigned int *)0x40023864) |
|
#define | RCC_APB2_BIT_SPI1 (1UL<<12) |
|
#define | SPI1_BASE 0x40013000 |
|
#define | SPI2_BASE 0x40003800 |
|
#define | SPI1 ((st_reg_spi *)SPI1_BASE) |
|
#define | SPI2 ((st_reg_spi *)SPI2_BASE) |
|
#define | SPI_CR1_BIT_BIDIMODE (1UL<<15) |
|
#define | SPI_CR1_BIT_BIDIOE (1UL<<14) |
|
#define | SPI_CR1_BIT_CRCEN (1UL<<13) |
|
#define | SPI_CR1_BIT_CRCNEXT (1UL<<12) |
|
#define | SPI_CR1_BIT_DFF (1UL<<11) |
|
#define | SPI_CR1_BIT_RXONLY (1UL<<10) |
|
#define | SPI_CR1_BIT_SSM (1UL<<9) |
|
#define | SPI_CR1_BIT_SSI (1UL<<8) |
|
#define | SPI_CR1_BIT_LSBFIRST (1UL<<7) |
|
#define | SPI_CR1_BIT_SPE (1UL<<6) |
|
#define | SPI_CR1_BIT_BR_256 (7UL<<3) |
|
#define | SPI_CR1_BIT_MSTR (1UL<<2) |
|
#define | SPI_CR1_BIT_CPOL (1UL<<1) |
|
#define | SPI_CR1_BIT_CPHA (1UL<<0) |
|
#define | SPI_CR2_BIT_TXEIE (1UL<<7) |
|
#define | SPI_CR2_BIT_RXNEIE (1UL<<6) |
|
#define | SPI_CR2_BIT_ERRIE (1UL<<5) |
|
#define | SPI_CR2_BIT_SSOE (1UL<<2) |
|
#define | SPI_CR2_BIT_TXDMAEN (1UL<<1) |
|
#define | SPI_CR2_BIT_RXDMAEN (1UL<<0) |
|
#define | SPI_SR_BIT_BSY (1UL<<7) |
|
#define | SPI_SR_BIT_OVR (1UL<<6) |
|
#define | SPI_SR_BIT_MODF (1UL<<5) |
|
#define | SPI_SR_BIT_CRCERR (1UL<<4) |
|
#define | SPI_SR_BIT_UDR (1UL<<3) |
|
#define | SPI_SR_BIT_CHSIDE (1UL<<2) |
|
#define | SPI_SR_BIT_TXE (1UL<<1) |
|
#define | SPI_SR_BIT_RXNE (1UL<<0) |
|
#define | SPI_I2SCFGR_BIT_I2SMOD (1UL<<11) |
|
#define | SPI_I2SCFGR_BIT_I2SE (1UL<<10) |
|
#define | SPI_I2SCFGR_BIT_I2SCFG (3UL<<8) |
|
#define | SPI_I2SCFGR_BIT_PCMSYNC (1UL<<7) |
|
#define | SPI_I2SCFGR_BIT_I2SSTD (3UL<<4) |
|
#define | SPI_I2SCFGR_BIT_CKPOLD (1UL<<3) |
|
#define | SPI_I2SCFGR_BIT_DATLEN (3UL<<1) |
|
#define | SPI_I2SCFGR_BIT_CHLEN (1UL<<0) |
|
#define | DMA1_BASE 0x40026000 |
|
#define | DMA2_BASE 0x40026400 |
|
#define | DMA1 ((st_reg_dma *)DMA1_BASE) |
|
#define | DMA2 ((st_reg_dma *)DMA2_BASE) |
|
#define | DMA_LISR_BIT_FEIF3 (1UL<<22) |
|
#define | DMA_LISR_BIT_TCIF3 (1UL<<27) |
|
#define | DMA_LISR_BIT_HTIF3 (1UL<<26) |
|
#define | DMA_LISR_BIT_TEIF3 (1UL<<25) |
|
#define | DMA_LISR_BIT_DMEIF3 (1UL<<24) |
|
#define | DMA_LISR_BIT_FEIF3 (1UL<<22) |
|
#define | DMA_LISR_BIT_TCIF2 (1UL<<21) |
|
#define | DMA_LISR_BIT_HTIF2 (1UL<<20) |
|
#define | DMA_LISR_BIT_TEIF2 (1UL<<19) |
|
#define | DMA_LISR_BIT_DMEIF2 (1UL<<18) |
|
#define | DMA_LISR_BIT_FEIF2 (1UL<<16) |
|
#define | DMA_HISR_BIT_TCIF4 (1UL<<5) |
|
#define | DMA_HISR_BIT_HTIF4 (1UL<<4) |
|
#define | DMA_HISR_BIT_TEIF4 (1UL<<3) |
|
#define | DMA_HISR_BIT_DMEIF4 (1UL<<2) |
|
#define | DMA_HISR_BIT_FEIF4 (1UL<<0) |
|
#define | DMA_SxCR_BIT_EN (1UL<<0) |
|
#define | DMA_SxCR_BIT_DMEIE (1UL<<1) |
|
#define | DMA_SxCR_BIT_TEIE (1UL<<2) |
|
#define | DMA_SxCR_BIT_HTIE (1UL<<3) |
|
#define | DMA_SxCR_BIT_TCIE (1UL<<4) |
|
#define | DMA_SxCR_BIT_PFCTRL (1UL<<5) |
|
#define | DMA_SxCR_BIT_DIR_ALL (3UL<<6) |
|
#define | DMA_SxCR_BIT_DIR_P2M (0UL<<6) |
|
#define | DMA_SxCR_BIT_DIR_M2P (1UL<<6) |
|
#define | DMA_SxCR_BIT_DIR_M2M (2UL<<6) |
|
#define | DMA_SxCR_BIT_CIRC (1UL<<8) |
|
#define | DMA_SxCR_BIT_PINC (1UL<<9) |
|
#define | DMA_SxCR_BIT_MINC (1UL<<10) |
|
#define | DMA_SxCR_BIT_PSIZE_ALL (3UL<<11) |
|
#define | DMA_SxCR_BIT_PSIZE_BYTE (0UL<<11) |
|
#define | DMA_SxCR_BIT_PSIZE_HW (1UL<<11) |
|
#define | DMA_SxCR_BIT_PSIZE_WORD (2UL<<11) |
|
#define | DMA_SxCR_BIT_MSIZE_ALL (3UL<<13) |
|
#define | DMA_SxCR_BIT_MSIZE_BYTE (0UL<<13) |
|
#define | DMA_SxCR_BIT_MSIZE_HW (1UL<<13) |
|
#define | DMA_SxCR_BIT_MSIZE_WORD (2UL<<13) |
|
#define | DMA_SxCR_BIT_MSIZE_PINCOS (1UL<<15) |
|
#define | DMA_SxCR_BIT_PL_ALL (3UL<<16) |
|
#define | DMA_SxCR_BIT_PL_LOW (0UL<<16) |
|
#define | DMA_SxCR_BIT_PL_MEDIUM (1UL<<16) |
|
#define | DMA_SxCR_BIT_PL_HIGH (2UL<<16) |
|
#define | DMA_SxCR_BIT_PL_VHIGH (3UL<<16) |
|
#define | DMA_SxCR_BIT_DBM (1UL<<18) |
|
#define | DMA_SxCR_BIT_CT (1UL<<19) |
|
#define | DMA_SxCR_BIT_PBURST_ALL (3UL<<21) |
|
#define | DMA_SxCR_BIT_PBURST_SINGLE (0UL<<21) |
|
#define | DMA_SxCR_BIT_PBURST_INCR4 (1UL<<21) |
|
#define | DMA_SxCR_BIT_PBURST_INCR8 (2UL<<21) |
|
#define | DMA_SxCR_BIT_PBURST_INCR16 (3UL<<21) |
|
#define | DMA_SxCR_BIT_MBURST_ALL (3UL<<23) |
|
#define | DMA_SxCR_BIT_MBURST_SINGLE (0UL<<23) |
|
#define | DMA_SxCR_BIT_MBURST_INCR4 (1UL<<23) |
|
#define | DMA_SxCR_BIT_MBURST_INCR8 (2UL<<23) |
|
#define | DMA_SxCR_BIT_MBURST_INCR16 (3UL<<23) |
|
#define | DMA_SxCR_BIT_CHSEL_ALL (7UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH0 (0UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH1 (1UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH2 (2UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH3 (3UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH4 (4UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH5 (5UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH6 (6UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_CH7 (7UL<<25) |
|
#define | DMA_SxCR_BIT_CHSEL_SHIFT (25) |
|
#define | DMA_SxFCR_BIT_FEIE (1UL<<7) |
|
#define | DMA_SxFCR_BIT_FS_ALL (7UL<<3) |
|
#define | DMA_SxFCR_BIT_DMDIS (1UL<<2) |
|
#define | DMA_SxFCR_BIT_FTH_ALL (3UL<<0) |
|
#define | DMA_SxFCR_BIT_FTH_1P4 (0UL<<0) |
|
#define | DMA_SxFCR_BIT_FTH_1P2 (1UL<<0) |
|
#define | DMA_SxFCR_BIT_FTH_3P4 (2UL<<0) |
|
#define | DMA_SxFCR_BIT_FTH_FULL (3UL<<0) |
|
#define | NVIC_ISER0 (*(volatile unsigned int *)0xE000E100) |
|
#define | NVIC_ISER1 (*(volatile unsigned int *)0xE000E104) |
|
#define | MUTEX_LOCK_TIMEOUT 1000 |
|
#define | SPI_RETRY_TIME 1000000 |
|
#define | SPI_WAIT_TIME 500 |
|
|
void | lock_spi (struct st_device *dev) |
|
void | unlock_spi (struct st_device *dev) |
|
static void | inthdr_spi1 (unsigned int intnum, void *sp) |
|
static void | inthdr_spi2 (unsigned int intnum, void *sp) |
|
static void | inthdr_spi_dma2 (unsigned int intnum, void *sp) |
|
static void | inthdr_spi_dma1 (unsigned int intnum, void *sp) |
|
static void | init_gpio (st_reg_gpio *gpio, int pin, int pup) |
|
static void | init_spi (struct st_device *dev) |
|
static int | init_driver (struct st_device *dev) |
|
static int | spi_readbyte (struct st_device *dev, unsigned char *rd) |
|
static int | spi_transblock (struct st_device *dev, unsigned char *rd, long size, int dir_read) |
|
static int | spi_write_cont_word (struct st_device *dev, unsigned short data, long size) |
|
static int | spi_writebyte (struct st_device *dev, unsigned char data) |
|
static int | spi_writeword (struct st_device *dev, unsigned short data) |
|
static int | spi_register (struct st_device *dev, char *param) |
|
static int | spi_getc (struct st_device *dev, unsigned char *rd) |
|
static int | spi_read (struct st_device *dev, void *data, unsigned int size) |
|
static int | spi_putc (struct st_device *dev, unsigned char ch) |
|
static int | spi_write (struct st_device *dev, const void *data, unsigned int size) |
|
static int | spi_ioctl (struct st_device *dev, unsigned int com, unsigned int arg, void *param) |
|
static int | spi_suspend (struct st_device *dev) |
|
static int | spi_resume (struct st_device *dev) |
|
STM32F4 SPIドライバ
- 日付
- 2013.04.06
- 著者
- Takashi SHUDO
- 覚え書き
SPI1 PA5 SPI1_SCK PA6 SPI1_MISO PA7 SPI1_MOSI RX DMA2_Stream2 TX DMA2_Stream3
SPI2 PB13 SPI2_SCK PB14 SPI2_MISO PB15 SPI2_MOSI RX DMA1_Stream3 TX DMA1_Stream4
spi.c に定義があります。